The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to techniques which are effective when applied to a semiconductor integrated circuit device having a multilayer wiring structure and a manufacturing method therefor.
In a semiconductor integrated circuit device having a multilayer wiring structure, after lower-layer wiring is formed, an insulator film is formed so as to cover the lower-layer wiring, and this insulator film is used as an inter-layer insulator film and is provided with a contact hole (or through hole), whereupon upper-layer wiring which is connected with the lower-layer wiring through the contact hole is formed. It is considered that the contact hole has its peripheral wall tapered in order to improve the step coverage of the upper-layer wiring.
The inventors made a study on a method of forming the upper-layer wiring in the semiconductor integrated circuit device having the tapered contact hole. The method is not a technique publicly known, but is a technique studied by the inventors, and it is outlined as follows: With the technique studied by the inventors, after lower-layer wiring of aluminum (Al) is formed, a silicon-dioxide (SiO.sub.2) film is formed on the whole area of the Al layer as an inter-layer insulator film, and it is provided with a tapered contact hole for connecting upper-layer wiring and the lower-layer wiring. Subsequently, the upper-layer wiring of aluminum is formed. The surface of the lower-layer wiring, however, is formed with an alumina (Al.sub.2 O.sub.3) film for the reason that the wiring material, aluminium has the property of liability to surface oxidation. Therefore, when the upper-layer wiring is formed under this state left intact, the continuity between the upper and lower wiring layers becomes inferior due to the alumina film which covers the surface of the lower-layer aluminum wiring exposed through the contact hole. In order to prevent this drawback, before the formation of the upper-layer wiring, sputter-etching is carried out thereby to remove the alumina (Al.sub.2 O.sub.3) film and to denude the surface of the aluminium wiring. Thereafter, the upper-layer wiring is formed.
Meanwhile, in the official gazette of Japanese Patent Application Laid-open No. 140720/ 1985, it is discussed that only the parts of the peripheral wall of a contact hole extending in the lengthwise direction of lower-layer wiring are provided with stair-like steps, thereby to enhance the step coverage of upper-layer wiring in the contact hole.